1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a memory cell for a dynamic random access memory (DRAM).
2. Description of the Prior Art
Conventionally, there has been constructed a dynamic random access memory (referred to as DRAM hereinafter) comprising a transistor and a capacitor. Accompanied by a highly densified integration, an area for the capacitor for storing a memory need be further made compact.
However, in accordance with a demand of a noise margin or sensitivity of a sense amplifier, there is certain limit in miniaturization thereof. Thus, the configuration of the capacitor is made three-dimensionally so as to increase a surface area thereof, so that an effective area viewed two-dimensionally can be reduced. This attempt has been made since the emergence of 1-4 mega DRAM.
However, the three dimensional configuration is complicated and a processing technique therefor to realize such configuration is extremely difficult. Then, there is proposed a gain cell in which there is provided a amplifying function in the cell itself. Among such gain cells, there is a memory cell where a gate capacity of a transistor is used for a capacitor serving to store an electric charge, and in order to read the electric charge, a charge level is amplified by providing the charge based on data (the stored charge) from a power supply line. In this gain cell, a large-area capacitor is not necessary and the stored charge is supplied from the power line regardless of the charge stored in the capacitor, so that miniaturization and large capacitance therefor can be realized.
FIG. 1 and FIG. 2 shows circuit diagrams for such DRAM. With reference to FIG. 1, the second MOSFET indicated with M2 is connected to the power line V.sub.DD, a source of M2 is connected to a drain of the first MOSFET indicated with M1, and the source of M1 is connected to a bit line BL. Furthermore, a gate of M1 is connected to a word line WL, and a switching element S is provided and connected between the gate of M2 and the drain of M1. FIG. 2 shows an example where there is used a Schottky diode as the switching element S shown FIG. 1. It is to be noted that M1 serves as an access transistor and M2 a storage transistor.
Next, the operation of the conventional DRAM shown in FIG. 1 an FIG. 2 will be described in detail.
First of all, when "1" (high potential) is to be written to the gain cell, an electric potential of a word line WL of M1 as a transfer transistor is made "1" (high potential) so as to be rendered conductive, and the gate capacitance of M2 which is charged and the storage transistor is made "1" (high potential) through the Schottky diode D. Thus, "1" is written. In this state, even if M1 is turned off, the charge is stored in the gate capacitance of M2, in other words, the data remains stored since the small current flows in a reverse direction through the Schottky diode D. On the other hand, for read-out, the electric potential of the word line WL of M2 is made "1", and if "1" is stored in M2 the M2 is in a conductive state so that the current flows through from the power line V.sub.DD to cause to increase the potential of bit line BL and "1" is read out. Namely, the gate capacitance of M2 is utilized as a storage capacitance and an amplifying operation of M2 is utilized so that an output charge is much greater than the charge stored in the cell.
However, in the above-mentioned highly integrated DRAM, since there is utilized a reverse-direction leak current of the diode, whose controllability is no so reliable, in order to extract the charge (rewriting from "1" state to "0" state), an operation margin of the cell is reduced, thus causing a problem where reliability of write-in data and controllability of write-in time are reduced.
With reference to FIG. 3, a similar disadvantage is presented where there is needed a capacity for storing a predetermined electric charge in the DRAM and thus there must be secured an area for such the capacitor. Therefore, the area required for the capacitor will be an disadvantageous aspect in terms of the miniaturization for the DRAM.
Moreover, when a desirable diode is used as the switching element, there takes much time to pull down the charge from the gate, thus being unable to realize a high-speed DRAM.